Principal Verification Engineer

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-based connectivity with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations.

As a Principal Verification Engineer on the ASIC & Networking team, you will support TeraWave's first in-house silicon program, which comprises a high-throughput modem and a DSP-intensive digital beamformer with first tapeout targeted for 2027. Verification strategy, methodology, and infrastructure are being defined now, and you will help define them.

The work spans IP, subsystem, and full SoC verification, including CPU subsystems, performance-critical interconnects, security, high-speed peripherals, modem datapath and PHY layers, DSP and beamforming compute, and mixed-signal interfaces. You will own a subset of this scope aligned to your background.

The team treats constrained-random simulation, formal methods, and processor-driven SoC testing as equal first-class tools, and is building an AI-enabled verification platform that includes LLM-assisted stimulus and testbench generation, automated regression triage and failure clustering, and data-driven coverage closure. Because none of this is inherited, the engineers who build these capabilities will own them - and grow with the program as it scales.

Background in wireless communications, modem, baseband, and DSP verification is welcome but not required. Architects and modeling engineers support your ramp, and verification judgment and system-level thinking are weighted above domain background.

Key Responsibilities

• Lead verification for chip level and complex subsystems through sign-off, collaborating with global engineering teams.
• Own verification strategy, test plans, and measurable coverage goals across assigned subsystems and SoC.
• Identify verification gaps, propose methodology changes, and implement them across the verification organization.
• Serve as subject area expert, setting technical direction and resolving escalated verification problems.
• Architect reusable verification environments, reference models, and infrastructure spanning IP, subsystem, and SoC levels.
• Drive regression health, coverage closure, and sign-off readiness across simulation and formal results.
• Review testbench architecture and debug approaches, and mentor engineers in verification methodology.
• Partner with design, architecture, and modeling teams to align verification with program milestones.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience.
• Minimum ten years of professional experience in ASIC or SoC functional verification.
• Hands-on expertise in SystemVerilog and UVM testbench development, plus metric driven verification.
• Experience as verification technical lead on at least one taped out silicon program.
• Willingness to travel up to 10 percent to other team locations.

Preferred Qualifications

• Recognized depth in at least one verification specialty applied on production silicon programs.
• Formal verification experience on production silicon, including connectivity, register maps, arbitration, CDC, or security properties.
• Gate level simulation experience, including timing aware and post layout runs and debug.
• Verification background in wireless or wired communication systems, including modem, baseband, PHY, or DSP hardware.
• Experience verifying LDPC, FEC, framing, or beamforming logic using bit-accurate reference models and fixed-point analysis.
• Experience developing C based or portable stimulus for SoC, CPU boot, and firmware driven scenarios.
• Experience applying AI, ML, or LLM tooling to stimulus generation, regression triage, or coverage analysis.